Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU101848" target="_blank" >RIV/00216305:26230/12:PU101848 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System
Original language description
This paper is focused to present the methods of design synchronization after the partial dynamic reconfiguration of FPGA and also there was introduced a new method inspired from one widely used.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
ISBN
978-3-902457-33-2
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
20-21
Publisher name
IEEE Computer Society
Place of publication
Cesme-Izmir
Event location
Izmir
Event date
Sep 5, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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