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Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU98170" target="_blank" >RIV/00216305:26230/12:PU98170 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DDECS.2012.6219037" target="_blank" >http://dx.doi.org/10.1109/DDECS.2012.6219037</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DDECS.2012.6219037" target="_blank" >10.1109/DDECS.2012.6219037</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

  • Original language description

    In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run thehardware (software) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual software load being monitored with no intrusion to the software. According to the actual software load it is able to buffer all interrupts and related data while the software is highly loaded and redirect the interrupts to the MCU as soon as the software becomes underloaded.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2012

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

  • ISBN

    978-1-4673-1188-5

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    121-126

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Tallin

  • Event location

    Tallinn

  • Event date

    Apr 18, 2012

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000312905700031