Automatic synthesis of small AdaBoost Classifier in FPGA

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106335" target="_blank" >RIV/00216305:26230/13:PU106335 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Automatic synthesis of small AdaBoost Classifier in FPGA

Original language description

Novel pre-processing units for AbaBoost classifiers are introduced which can improve performance and reduce power consumption in many image processing applications. An approach for automatic classifier synthesis to the FPGA is also described. The introduced classification architecture is intensively saving processing resources and very fast as well. Several optimization techniques that are used in the process of automatic synthesis are also shown.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/ED1.1.00%2F02.0070" target="_blank" >ED1.1.00/02.0070: IT4Innovations Centre of Excellence</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2013

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2013

ISBN

978-1-4673-6133-0

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

1-6

Publisher name

IEEE Computer Society

Place of publication

Brno

Event location

Karlovy Vary

Event date

Apr 8, 2013

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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