New Methods for Increasing Efficiency and Speed of Functional Verification

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106451" target="_blank" >RIV/00216305:26230/13:PU106451 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

New Methods for Increasing Efficiency and Speed of Functional Verification

Original language description

This paper describes one approach for verification of hardware systems called functional verification. Several challenges and problems connected with efficiency and speed of functional verification are identified and reflected in the goals of the Ph.D. thesis. The first goal deals with creation of a complete coverage model of the verified system depending on the measurable attributes of a circuit. The second one aims at finding new methods how to check specific values of such attributes as fast as possible and to increase the overall efficiency of functional verification.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

20206 - Computer hardware and architecture

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2013

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Počítačové architektury a diagnostika PAD 2013

ISBN

978-80-261-0270-0

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

111-116

Publisher name

University of West Bohemia in Pilsen

Place of publication

Plzeň

Event location

Teplá

Event date

Sep 9, 2013

Type of event by nationality

CST - Celostátní akce

UT code for WoS article

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