ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APR27655" target="_blank" >RIV/00216305:26230/14:PR27655 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/prod/index.php?id=381" target="_blank" >http://www.fit.vutbr.cz/research/prod/index.php?id=381</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays
Original language description
ZyEHW is a joint hardware-software project for evolutionary design in the Xilinx Zynq-7000 field-programmable gate array. It contains (1) the hardware descriptions of the evolutionary design framework implemented in the programmable logic, (2) the software for both ARM processors of the Zynq platform and (3) the software required for generating the inputs and processing the outputs of the evolutionary design framework.The evolutionary design framework is based on our developed architecture where the candidate solutions can be established and mutated by fine-grained partial reconfiguration of look-up tables. Our advanced control unit and the reduced routing ensures that six candidate solutions can be evaluated in parallel (in a XC7Z020 device) and at avery high operational frequency (a larger device would allow to evaluate even more candidate solutions in parallel).The program code is deployed into one of the processors of Zynq-7000 and the evolutionary design framework into its progra
Czech name
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Czech description
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Classification
Type
R - Software
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA14-04197S" target="_blank" >GA14-04197S: Advanced Methods for Evolutionary Design of Complex Digital Circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Internal product ID
ZyEHW
Technical parameters
Volně šiřitelný software poskytovaný pod "GNU General Public License, either version 3 or any later version".ZyEHW zahrnuje: 1. popis hardwaru (jazykem VHDL) implementovaný v programovatelné logice, 2. software (v jazyku C) pro obě ARM procesory dostupné na Zynq platformě a 3. software (v jazyku C) pro generovaní vstupů a zpracování výstupů evolučního návrhového systému. Systémové požadavky: - vývojová deska s Xilinx Zynq-7000, - Xilinx Vivado Design Suite pro syntézu hardwaru (stačí bezplatná licence), - gcc, make, ffmpeg, libxml2 a libtiff pro generovaní vstupů a zpracování výstupů evolučního návrhového systému.
Economical parameters
Volně šiřitelný software poskytovaný pod "GNU General Public License, either version 3 or any later version".
Owner IČO
00216305
Owner name
Vysoké učení technické v Brně