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On NFA-Split Architecture Optimizations

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APU111928" target="_blank" >RIV/00216305:26230/14:PU111928 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DDECS.2014.6868808" target="_blank" >http://dx.doi.org/10.1109/DDECS.2014.6868808</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DDECS.2014.6868808" target="_blank" >10.1109/DDECS.2014.6868808</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    On NFA-Split Architecture Optimizations

  • Original language description

    The NFA-Split architecture is an efficient approach to the mapping of regular expressions to the FPGA. However, the NFA-Split architecture has some drawbacks. The most significant are the high time complexity due to usage of determinisation to detect simultaneously active states. The other one is in some cases high consumption of BRAMs. The paper presents solutions of those drawbacks. According to the results up to 39 times overall speedup of  construction of the NFA-Split architecture was achieved. Reduction of utilized BRAMs is up to 97%.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/ED1.1.00%2F02.0070" target="_blank" >ED1.1.00/02.0070: IT4Innovations Centre of Excellence</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2014

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

  • ISBN

    978-1-4799-4558-0

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    274-277

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Warsaw

  • Event location

    Warsaw

  • Event date

    Apr 23, 2014

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article