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State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APU112047" target="_blank" >RIV/00216305:26230/14:PU112047 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DSD.2014.103" target="_blank" >http://dx.doi.org/10.1109/DSD.2014.103</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DSD.2014.103" target="_blank" >10.1109/DSD.2014.103</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

  • Original language description

    The paper is focused on the state synchronization issue for a fault-tolerant systems implemented into SRAM-based FPGA after repairing of detected failure. Fault-tolerant systems often use HW redundancy to increase their reliability and partial dynamic reconfiguration of FPGA to repair the part of configuration memory with copy of the protected circuit where the failure was detected. In the paper, implemented fault-tolerant system which integrates previously developed reconfiguration controller and CAN bus control system is described. Then, generic architecture for the synchronization is proposed and synchronization methods for given fault-tolerant system are implemented.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2014

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    17th Euromicro Conference on Digital Systems Design

  • ISBN

    978-0-7695-5074-9

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    704-707

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Verona

  • Event location

    Verona

  • Event date

    Aug 27, 2014

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000358409000100