Fast Simulation of Pipeline in ASIP simulators
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APU112174" target="_blank" >RIV/00216305:26230/14:PU112174 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/MTV.2014.18" target="_blank" >http://dx.doi.org/10.1109/MTV.2014.18</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/MTV.2014.18" target="_blank" >10.1109/MTV.2014.18</a>
Alternative languages
Result language
angličtina
Original language name
Fast Simulation of Pipeline in ASIP simulators
Original language description
A fast and accurate simulator of the newly designed application specific instruction-set processors is essential during processor development, testing, and verification as well as for software development. Instruction-set simulators are usually used at the early stages of the design. They have good performance, but because of their low accuracy they cannot be used for a detailed pipeline or timing analysis. For this task, cycle-accurate simulators are used. They are of high accuracy since the whole microarchitecture is simulated. But at the same time, the simulation time can be significantly longer than in the case of instruction-set simulators. We present a technique which reduces the simulation time with an acceleration of pipeline simulation. Experimental results show a speed-up during simulation. Moreover, the proposed concept can also be used for hardware realization of application specific instruction-set processors.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
15th International Workshop on Microprocessor Test and Verification
ISBN
978-0-7695-4000-9
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
1-6
Publisher name
IEEE Computer Society
Place of publication
Austin
Event location
Austin, TX
Event date
Dec 15, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000380373200003