Modeling and Analysis of Fault-Tolerant Systems by Means of UPPAAL SMC: Method and Benefits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121589" target="_blank" >RIV/00216305:26230/16:PU121589 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=11073" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=11073</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Modeling and Analysis of Fault-Tolerant Systems by Means of UPPAAL SMC: Method and Benefits
Original language description
The paper presents a method of modeling and analysis of fault-tolerant (FT) electronic systems by means of a novel statistical model checking (SMC) approach available in the UPPAAL SMC tool. The method can be seen as an alternative to classical analytic approaches based on instruments such as fault-tree or Markov reliability models of the above-specified systems. Main goal of the paper is to show that - taking the advantage of SMC - the reliability analysis of systems can be facilitated even for adverse conditions such as inconstant failure (hazard) rate of inner system components. In the paper, basic terms and principles related to modeling and analysis of FT systems are summarized, followed by a short introduction to the UPPAAL SMC tool, its practical applicability to analysis and modeling of basic FT systems and evaluation of the results achieved on basis of the tool.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Informal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
ISBN
978-80-8086-256-5
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
32-37
Publisher name
Slovak University of Technology in Bratislava
Place of publication
Bratislava
Event location
Košice
Event date
Apr 20, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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