Implementation of Fault Tolerant Techniques into FPNNs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU123093" target="_blank" >RIV/00216305:26230/16:PU123093 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/FPT.2016.7929559" target="_blank" >http://dx.doi.org/10.1109/FPT.2016.7929559</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/FPT.2016.7929559" target="_blank" >10.1109/FPT.2016.7929559</a>
Alternative languages
Result language
angličtina
Original language name
Implementation of Fault Tolerant Techniques into FPNNs
Original language description
This paper presents concepts of FPNN which can be used for the implementation of artificial neural networks in FPGAs and introduces fault tolerant techniques applied on this concept that are developed by the authors.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2016 International Conference on Field Programmable Technology
ISBN
978-1-5090-5602-6
ISSN
—
e-ISSN
—
Number of pages
2
Pages from-to
297-298
Publisher name
IEEE Computer Society
Place of publication
Xi'an
Event location
Xi'an
Event date
Dec 7, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000402988900055