Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126407" target="_blank" >RIV/00216305:26230/17:PU126407 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11420/" target="_blank" >https://www.fit.vut.cz/research/publication/11420/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ICCAD.2017.8203807" target="_blank" >10.1109/ICCAD.2017.8203807</a>
Alternative languages
Result language
angličtina
Original language name
Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished
Original language description
We present a novel method allowing one to approximate complex arithmetic circuits with formal guarantees on the approximation error. The method integrates in a unique way formal techniques for approximate equivalence checking into a search-based circuit optimisation algorithm. The key idea of our approach is to employ a novel search strategy that drives the search towards promptly verifiable approximate circuits. The method was implemented within the ABC tool and extensively evaluated on functional approximation of multipliers (with up to 32-bit operands) and adders (with up to 128-bit operands). Within a few hours, we constructed a high-quality Pareto set of 32-bit multipliers providing trade-offs between the circuit error and size. This is for the first time when such complex approximate circuits with formal error guarantees have been derived, which demonstrates an outstanding performance and scalability of our approach compared with existing methods that have either been applied to the approximation of multipliers limited to 8-bit operands or statistical testing has been used only. Our approach thus significantly improves capabilities of the existing methods and paves a way towards an automated design process of provably-correct circuit approximations.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD)
ISBN
978-1-5386-3093-8
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
416-423
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Irvine, CA
Event location
Irvine, CA
Event date
Nov 13, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000424863100055