Automation of Processor Verification Using Recurrent Neural Networks
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU130683" target="_blank" >RIV/00216305:26230/17:PU130683 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8396943" target="_blank" >https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8396943</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/MTV.2017.15" target="_blank" >10.1109/MTV.2017.15</a>
Alternative languages
Result language
angličtina
Original language name
Automation of Processor Verification Using Recurrent Neural Networks
Original language description
When considering simulation-based verification of processors, the current trend is to generate stimuli using pseudo-random generators (PRGs), apply them to the processor inputs and monitor the achieved coverage of its functionality in order to determine verification completeness. Stimuli can have different forms, for example, they can be represented by bit vectors applied to the input ports of the processor or by programs that are loaded directly into the program memory. In this paper, we propose a new technique dynamically altering constraints for PRG via recurrent neural network, which receives a coverage feedback from the simulation of design under verification. For the demonstration purposes we used processors provided by Codasip as their coverage state space is reasonably big and differs for various kinds of processors. Nevertheless, techniques presented in this paper are widely applicable. The results of experiments show that not only the coverage closure is achieved much sooner, but we are able to isolate a small set of stimuli with high coverage that can be used for running regression tests.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
18th International Workshop on Microprocessor and SOC Test, Security and Verification (MTV)
ISBN
978-1-5386-3351-9
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
15-20
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Austin, Texas
Event location
Austin, Texas
Event date
Dec 11, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000455129000004