Pipelined ALU for effective external memory access in FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU139367" target="_blank" >RIV/00216305:26230/20:PU139367 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21240/20:00342829 RIV/63839172:_____/20:10133299
Result on the web
<a href="https://ieeexplore.ieee.org/abstract/document/9217822" target="_blank" >https://ieeexplore.ieee.org/abstract/document/9217822</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD51259.2020.00026" target="_blank" >10.1109/DSD51259.2020.00026</a>
Alternative languages
Result language
angličtina
Original language name
Pipelined ALU for effective external memory access in FPGA
Original language description
The external memories in digital design are closely related to high response time. The most common approach to mitigate latency is adding a caching mechanism into the memory subsystem. This solution might be sufficient in CPU architecture, where we can reschedule operations when a cache miss occurs. However, the FPGA architectures are usually accelerators with simple functionality, where it is not possible to postpone work. The cache miss often leads to whole pipeline stall or even to data loss. The architecture we present in this paper reduces this problem by aggregating arithmetic operations into the memory subsystem itself. Fast data processing is achieved because arithmetic operations working with external data are offloaded. Our architecture reaches a speed of 200 Mp/s (operations carried out). It is designed to be used in systems with link speeds of 100 Gb/s. It outperforms other implementations by a factor of at least 3. The additional benefit of our architecture is reducing the number of memory transactions by a factor of two on real-world datasets.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2020 23RD EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2020)
ISBN
978-1-7281-9535-3
ISSN
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e-ISSN
—
Number of pages
4
Pages from-to
97-100
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Kranj
Event location
Portorož, Slovenia, Grand Hotel Bernardin
Event date
Aug 26, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000630443300015