AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F26%3A0194216" target="_blank" >RIV/00216305:26230/26:0194216 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/ISCAS56072.2025.11043775" target="_blank" >http://dx.doi.org/10.1109/ISCAS56072.2025.11043775</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISCAS56072.2025.11043775" target="_blank" >10.1109/ISCAS56072.2025.11043775</a>
Alternative languages
Result language
angličtina
Original language name
AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs
Original language description
The increasing demand for energy-efficient solutions has led to the emergence of an approximate computing paradigm that enables power-efficient implementations in various application areas such as image and data processing. The median filter, widely used in image processing and computer vision, is of immense importance in these domains. We propose a systematic design methodology for the design of power-efficient median networks suitable for on-chip or FPGA-based implementations. A search-based design method is used to obtain approximate medians that show the desired trade-offs between accuracy, power consumption and area on chip. A new metric tailored to this problem is proposed to quantify the accuracy of approximate medians. Instead of the simple error rate, our method analyses the rank error. A significant improvement in implementation cost is achieved. For example, compared to the well-optimized high-throughput implementation of the exact 9-input median, a 30% reduction in area and a 36% reduction in power consumption was achieved by introducing an error by one position (i.e., allowing the 4th or 6th lowest input to be returned instead of the median).
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/GA24-10990S" target="_blank" >GA24-10990S: Hardware-Aware Machine Learning: From Automated Design to Innovative and Explainable Solutions</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2025
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
ISBN
979-8-3503-5683-0
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
1-5
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
London
Event location
London
Event date
May 25, 2025
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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