An Efficient Deterministic test Pattern Compaction Scheme Using Modified IC Scan Chain
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F00%3A00000029" target="_blank" >RIV/46747885:24220/00:00000029 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
An Efficient Deterministic test Pattern Compaction Scheme Using Modified IC Scan Chain
Original language description
An Efficient Deterministic test Pattern Compaction Scheme Using Modified IC Scan Chain
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/VS96006" target="_blank" >VS96006: Study of electromechanical properties of materials and their use in science and technology</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2000
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proc. of IEEE European Test Workshop (ETW´00)
ISBN
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ISSN
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e-ISSN
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Number of pages
2
Pages from-to
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Publisher name
IEEE
Place of publication
Lisbon (Portugal)
Event location
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Event date
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Type of event by nationality
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UT code for WoS article
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