Low Hardware Overhead Deterministic Logic Test Pattern Generator
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F01%3A00000024" target="_blank" >RIV/46747885:24220/01:00000024 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Low Hardware Overhead Deterministic Logic Test Pattern Generator
Original language description
The article describes Low Hardware Overhead Deterministic Logic Test Pattern Generator
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F01%2F0566" target="_blank" >GA102/01/0566: Built-in self test equipment optimisation methods in integrated circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2001
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proc of ECM2S
ISBN
80-7083-444-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
137-140
Publisher name
Université Paul Sabatier Toulouse
Place of publication
Toulouse, France
Event location
Toulouse, France
Event date
May 30, 2001
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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