Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F08%3A%230001191" target="_blank" >RIV/46747885:24220/08:#0001191 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits

Original language description

The paper is about Implementation of Dynamically Reconfigurable Test Archtecture for FPGA Circuits

Czech name

Implementace dynamicky rekonfigurovatelné testovací architektury pro FPGA obvody

Czech description

Článek je o implementaci dynamicky rekonfigurovatelné testovací architektury pro FPGA obvody

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/1QS108040510" target="_blank" >1QS108040510: Technology for improving the testability of modern digital circuits</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2008

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

ISBN

978-1-4244-2276-0

ISSN

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e-ISSN

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Number of pages

5

Pages from-to

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Publisher name

IEEE

Place of publication

Slovakia

Event location

Bratislava

Event date

Jan 1, 2008

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000256936300039