Evolvable Hardware Implemented by FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F09%3A00503904" target="_blank" >RIV/49777513:23220/09:00503904 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Evolvable Hardware Implemented by FPGA
Original language description
This paper deals with the implementation of the evolvable hardware by FPGA devices. The present work examines the dependence of particular aspects of the genetic algorithm for the evolvable hardware domain usage. Practical implementation of this algorithm by the FPGA circuit is researched as well. In the paper, two practical examples of evolvable circuits are shown ? the combinational logic circuit and the evolutionary FIR filter.
Czech name
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Czech description
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Classification
Type
C - Chapter in a specialist book
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Book/collection name
Computer Applications in Electrical Engineering
ISBN
978-83-89333-33-9
Number of pages of the result
18
Pages from-to
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Number of pages of the book
306
Publisher name
COMPRINT
Place of publication
Poznan
UT code for WoS chapter
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