Frequency Synthesizer Based on Charge Balancing
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F13%3A43924959" target="_blank" >RIV/49777513:23220/13:43924959 - isvavai.cz</a>
Result on the web
<a href="http://dsp2013.dspconferences.org/" target="_blank" >http://dsp2013.dspconferences.org/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ICDSP.2013.6622674" target="_blank" >10.1109/ICDSP.2013.6622674</a>
Alternative languages
Result language
angličtina
Original language name
Frequency Synthesizer Based on Charge Balancing
Original language description
This article presents a design of new principle of the fractional frequency synthesizer based on charge balancing for spurious phase modulation suppression when pulses are periodically removed from pulse train. The new synthesizer can be used also as a universal building block in phase locked loop frequency synthesizers. The mathematical analysis and simulations of the system are also presented.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/ED2.1.00%2F03.0094" target="_blank" >ED2.1.00/03.0094: Regional Innovation Centre for Electrical Engineering (RICE)</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2013 18th International Conference on Digital Signal Processing (DSP)
ISBN
978-1-4673-5805-7
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
1-6
Publisher name
IEEE
Place of publication
Piscataway
Event location
Santorini, Řecko
Event date
Jul 1, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000343676800007