Fully parallel FPGA decoder for irregular LDPC codes
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F15%3A43926822" target="_blank" >RIV/49777513:23220/15:43926822 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Fully parallel FPGA decoder for irregular LDPC codes
Original language description
One of the most significant current discussions in error correction coding is on the replacement of state-of-the- art codes by new innovative solutions. We propose a scalable parallel FPGA architecture for LDPC decoding. Regular and irregular codes are supported by the presented architecture. The architecture can be easily utilized in hardware applications. The performance of synthetized decoders is presented.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of Papers : 2015 23rd Telecommunications Forum (TELFOR 2015)
ISBN
978-1-5090-0055-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
309-312
Publisher name
IEEE
Place of publication
Piscataway
Event location
Bělehrad, Srbsko
Event date
Nov 24, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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