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Non-Stationary Statistical Simulation of Blind-Oversampling CDR Circuits

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F60162694%3AG43__%2F13%3A00498779" target="_blank" >RIV/60162694:G43__/13:00498779 - isvavai.cz</a>

  • Alternative codes found

    RIV/00216305:26220/13:PU105876

  • Result on the web

    <a href="http://vavtest.unob.cz/registr" target="_blank" >http://vavtest.unob.cz/registr</a>

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Non-Stationary Statistical Simulation of Blind-Oversampling CDR Circuits

  • Original language description

    Statistical approach is the only practical set of methods for reliable simulation of Clock and Data Recovery circuits which operate at low bit-error rates. The paper deals with a statistical simulation model for blind-oversampling CDR circuits, which estimate the center of the data eye by counting the edges in several subintervals that divide the signal period. In the steady-state, the process is described by the multinomial distribution. The developed model simulates the estimation process in the non-stationary case, which allows including sinusoidal jitter, and frequency offset. Some simulation results are presented.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JA - Electronics and optoelectronics

  • OECD FORD branch

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Others

  • Publication year

    2013

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of 2013 IEEE Fourth Latin American Symposium on Circuits and Systems (LASCAS 2013)

  • ISBN

    978-1-4244-9485-9

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    1-4

  • Publisher name

    IEEE

  • Place of publication

    Cusco, Peru

  • Event location

    Cusco, Peru

  • Event date

    Jan 1, 2013

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000324855900067