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Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F60162694%3AG43__%2F18%3A00535388" target="_blank" >RIV/60162694:G43__/18:00535388 - isvavai.cz</a>

  • Alternative codes found

    RIV/00216305:26220/18:PU128687

  • Result on the web

    <a href="http://dx.doi.org/10.1109/SMACD.2018.8434846" target="_blank" >http://dx.doi.org/10.1109/SMACD.2018.8434846</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/SMACD.2018.8434846" target="_blank" >10.1109/SMACD.2018.8434846</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms

  • Original language description

    A procedure supporting the design and optimization of analog circuits is described. It is based on symbolic analysis of the respective linearized model with the aim of revealing the major factors influencing the non-ideal behavior of the designed device. SNAP 3, a powerful tool for the approximate symbolic analysis of circuits containing assorted types of active building blocks, plays a key role in this process. The procedure is illustrated on the example of inductance multiplier.

  • Czech name

    —

  • Czech description

    —

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    —

  • OECD FORD branch

    20201 - Electrical and electronic engineering

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    S - Specificky vyzkum na vysokych skolach<br>I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Others

  • Publication year

    2018

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018)

  • ISBN

    978-1-5386-5152-0

  • ISSN

    —

  • e-ISSN

    —

  • Number of pages

    4

  • Pages from-to

    265-268

  • Publisher name

    IEEE

  • Place of publication

    USA

  • Event location

    Praha

  • Event date

    Jul 2, 2018

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    —