Software Phase Lock Loops Applied in Three-Phase PWM Rectifier
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61388998%3A_____%2F11%3A00365382" target="_blank" >RIV/61388998:_____/11:00365382 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Software Phase Lock Loops Applied in Three-Phase PWM Rectifier
Original language description
Three SPLL (Software Phase Lock Loops)that differ by the method of the detection of symmetrical grid voltage sequences (positive and negative ones) are presented. Simulation and experimental results of these SPLL applied in a three-phase PWM rectifier connected to an unsymmetrical grid voltage system with harmonics are discussed, even under some disturbances and parameter changes of the grid. The function of the DSC (Delayed Signal Cancellation) based SPLL in PWM rectifier with fs = 1600 Hz was experimetally verified under different grid voltage disturbances with satisfactory results.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/FR-TI1%2F330" target="_blank" >FR-TI1/330: *Control system for high power electric converters</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Electrical Drives and Power Electronics - EDPE 11
ISBN
978-80-553-0734-3
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
227-232
Publisher name
Technical University of Košice
Place of publication
Košice
Event location
Stará Lesná, The High Tatras
Event date
Oct 28, 2011
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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