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The ATM Switch and Header Error Control FPGA Implementation

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27240%2F00%3A00010815" target="_blank" >RIV/61989100:27240/00:00010815 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    The ATM Switch and Header Error Control FPGA Implementation

  • Original language description

    Výsledky výzkumného projektu,který probíhal v rámci doktorského studia v oboru technická kybernetika a podpory projektu výzkumného grantového úkolu GAČR 102/98/1003 "Research and Development of Built-in Diagnostics Means of Integrated Circuits" zahrnujedílčí výsledky za rok 2000.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JD - Use of computers, robotics and its application

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GA102%2F98%2F1003" target="_blank" >GA102/98/1003: Research and application of built-in self test equipment in integrated circuits</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2000

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    IFAC Workshop PDS 2000

  • ISBN

    0-08-043620 X

  • ISSN

  • e-ISSN

  • Number of pages

    5

  • Pages from-to

  • Publisher name

    PERGAMON /Elsevier Science/

  • Place of publication

    Great Britain

  • Event location

  • Event date

  • Type of event by nationality

  • UT code for WoS article