Modelling VLSI Circuits Using Taylor Series

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27740%2F17%3A10237444" target="_blank" >RIV/61989100:27740/17:10237444 - isvavai.cz</a>

Result on the web

<a href="http://aip.scitation.org/doi/abs/10.1063/1.4992513" target="_blank" >http://aip.scitation.org/doi/abs/10.1063/1.4992513</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1063/1.4992513" target="_blank" >10.1063/1.4992513</a>

Result language

angličtina

Original language name

Modelling VLSI Circuits Using Taylor Series

Original language description

The paper introduces the capacitor substitution for CMOS logic gates, i.e. NANDs, NORs and inverters. It reveals the necessity of a very accurate and fast method for solving this problem. Therefore the Modern Taylor Series Method (MTSM) is used which provides an automatic choice of a higher order during the computation and a larger integration step size while keeping desired accuracy.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2017

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

AIP Conference Proceedings. Volume 1863

ISBN

978-0-7354-1538-6

ISSN

0094-243X

e-ISSN

neuvedeno

Number of pages

4

Pages from-to

"340006-1"-"340006-4"

Publisher name

American Institute of Physics

Place of publication

Melville

Event location

Rhodos

Event date

Sep 19, 2016

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000410159800340