High-Level Synthesis for FPGA

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27740%2F23%3A10253682" target="_blank" >RIV/61989100:27740/23:10253682 - isvavai.cz</a>

Result on the web

<a href="https://events.it4i.cz/event/206/" target="_blank" >https://events.it4i.cz/event/206/</a>

DOI - Digital Object Identifier

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Result language

angličtina

Original language name

High-Level Synthesis for FPGA

Original language description

The course aim was to demonstrate how to describe, debug, and implement application-specific accelerators on FPGA using the C/C++ language, rather than hardware description languages (e.g., VHDL or Verilog). Through simple examples, participants learned how to write kernels that can be synthesized on FPGA fabric, transfer data between the host and an FPGA board, and employ various optimization techniques to make the design more efficient in terms of speed and resource utilization. Leveraging the capabilities of HLS, they developed an accelerator for Cholesky matrix decomposition, utilizing the C/C++ programming language, along with the OpenCL and XRT libraries for development on AMD-Xilinx FPGAs. While the workshop primarily targeted AMD-Xilinx FPGA boards, the principles and insights garnered can readily be applied to FPGAs from various other vendors.

Czech name

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Czech description

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Type

O - Miscellaneous

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/MC2301" target="_blank" >MC2301: National Competence Centres in the framework of EuroHPC Phase 2 - EUROCC 2</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2023

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů