Packet Analysis for IPv6 Router Implemented by a PCI Acceleration Card

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F03%3A00000071" target="_blank" >RIV/63839172:_____/03:00000071 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Packet Analysis for IPv6 Router Implemented by a PCI Acceleration Card

Original language description

This document concerns the development of the Combo6 card that aims at accelerating IPv6 and IPv4 routing. Three main processing blocks are distinguished in its architecture: packet parsing blocks, header matching blocks and output blocks. My work consists of several tools dealing with the simulation of packet parsing blocks. These tools provide possibilities for simulation, testing and developing algorithms for the hardware. Further, outputs of these tools may be used for simulation and testing of header matching blocks, even parallel simulation of packet parsing blocks and header matching blocks is possible.

Czech name

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Czech description

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Type

A - Audiovisual production

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2003

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

ISBN

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Place of publication

Brno

Publisher/client name

CESNET z.s.p.o.

Version

CESNET technical report number 5/2003

Carrier ID

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