Scalable Embedded Architecture for High-speed Video Transmissions and Processing

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F11%3A00007202" target="_blank" >RIV/63839172:_____/11:00007202 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Scalable Embedded Architecture for High-speed Video Transmissions and Processing
Original language description
In this paper, we present a scalable and extendable hardware architecture for processing and transfer of ultra-high-definition video over high-speed 10/40/100Gbit networks with very low latency. We implemented this architecture in a single FPGA device. Data processing is divided between FPGA resources and an embedded operating system. The FPGA resources can be moved between various processing functions depending on the device mode. The resulting inexpensive and compact device is intended for high quality video transfers and processing with a low latency and to support deployment in education and remote venues.
Czech name
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Czech description
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Project
<a href="/en/project/TA01010324" target="_blank" >TA01010324: High-definition video transmissions over optical networks</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
ICSNC 2011, The Sixth International Conference on Systems and Networks Communications
ISBN
978-1-61208-166-3
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
161-166
Publisher name
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Place of publication
Barcelona, Spain
Event location
Barcelona, Spain
Event date
Oct 23, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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