Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F14%3A10130393" target="_blank" >RIV/63839172:_____/14:10130393 - isvavai.cz</a>
Alternative codes found
RIV/00216305:26230/14:PU112050
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring
Original language description
Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, itis also necessary to achieve rapid development cycle to provide fast response to security threats. We propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. The concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. The monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. This arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014)
ISBN
978-3-00-044645-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
264-267
Publisher name
IEEE Circuits and Systems Society
Place of publication
Munich, Germany
Event location
Munich, Germany
Event date
Sep 2, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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