DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F25%3A10133730" target="_blank" >RIV/63839172:_____/25:10133730 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/FPL68686.2025.00047" target="_blank" >http://dx.doi.org/10.1109/FPL68686.2025.00047</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/FPL68686.2025.00047" target="_blank" >10.1109/FPL68686.2025.00047</a>
Alternative languages
Result language
angličtina
Original language name
DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAs
Original language description
Achieving the lowest possible communication latency between an FPGA accelerator card and host CPU software is critical for many applications, such as high-frequency trading, in-memory storage systems, and 5G processing. However, no freely available PCIe DMA engine (DMAE) is currently optimized for low latency. To address this, we present DMA Calypte, an open-source, platform-independent, ultra-low-latency DMAE. We implemented numerous optimizations at the DMAE, software, and device driver levels to minimize communication latency over PCIe. DMA Calypte's functionality was validated on accelerator cards featuring AMD Kintex UltraScale+ and Agilex 7 F-Series chips with a PCIe Gen3 x8 interface. We achieved a round-trip time between software and FPGA of just 790 ns and a throughput of up to 35 Gbps.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/FW03010350" target="_blank" >FW03010350: Acceleration platform for low-latency trading</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2025
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2025 35th International Conference on Field-Programmable Logic and Applications (FPL)
ISBN
979-8-3315-9153-3
ISSN
1946-1488
e-ISSN
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Number of pages
5
Pages from-to
291-295
Publisher name
IEEE Xplore
Place of publication
Leiden
Event location
Leiden, Netherlands
Event date
Sep 1, 2025
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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