Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic.
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F01%3A16010124" target="_blank" >RIV/67985556:_____/01:16010124 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic.
Original language description
The LNS implementation of the Error-Feedback RLS Lattice algorithm in FPGA offers better speed than C30/C40 DSP floating-point and provides low- cost, efficient solution for different system on chip applications. We have demonstrated, that one can managewithout a dedicated DSP processor.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2001
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Advances in Systems Science: Measurement, Circuits and Control. Proceedings.
ISBN
960-8052-39-4
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
517-521
Publisher name
WSES Press
Place of publication
Rethymno
Event location
Kréta [GR]
Event date
Jul 8, 2001
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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