Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1.

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F01%3A16010125" target="_blank" >RIV/67985556:_____/01:16010125 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1.

Original language description

Implementation of IEEE floating point in FPGA (Field Programmable Gate Array)is not easy and therefore many advanced DSP and control algorithms make it to FPGA with considerable delays. This paper presents one of possible solution based on a 32-bit logarithmic ALU, in the form of an FPGA core compatible with the Handel C 2.1 and the new DK1 tool from Celoxica. This research is performed under the EU ESPRIT 33544 HSLA Long-term research project, coordinated by the University of Newcastle.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/LN00B096" target="_blank" >LN00B096: Center for Applied Cybernetics</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2001

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Celoxica User Conference. Proceedings.

ISBN

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ISSN

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e-ISSN

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Number of pages

1

Pages from-to

"X1"-"X5"

Publisher name

Celoxica

Place of publication

Abington

Event location

Stratford [GB]

Event date

Apr 2, 2001

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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