Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F11%3A00357150" target="_blank" >RIV/67985556:_____/11:00357150 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
Original language description
We analyse an impact of long-latency instructions, the family blocksize parameter, and the thread switch modifier on execution efficiency of families of threads in a single-core configuration of the UTLEON3 processor that implements the SVP microthreading model. The analysis is supported by code execution in an FPGA implementation of the processor. The conclusions drawn in this paper can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/7E08013" target="_blank" >7E08013: Architecture Paradigms and Programming Languages for Efficient programming of multiple COREs</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Architecture of Computing Systems - ARCS 2011
ISBN
978-3-642-19136-7
ISSN
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e-ISSN
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Number of pages
12
Pages from-to
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Publisher name
Springer-Verlag Berlin Heidelberg
Place of publication
Berlin
Event location
Camo
Event date
Feb 24, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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