ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F19%3A00499963" target="_blank" >RIV/67985556:_____/19:00499963 - isvavai.cz</a>
Result on the web
<a href="https://link.springer.com/article/10.1007%2Fs11265-018-1424-1" target="_blank" >https://link.springer.com/article/10.1007%2Fs11265-018-1424-1</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/s11265-018-1424-1" target="_blank" >10.1007/s11265-018-1424-1</a>
Alternative languages
Result language
angličtina
Original language name
ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA
Original language description
The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/7H14004" target="_blank" >7H14004: ALMARVI - Algorithms, Design Methods, and Many-Core Execution Platform for Low-Power Massive Data-Rate Video and Image Processing</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
Journal of Signal Processing Systems for Signal Image and Video Technology
ISSN
1939-8018
e-ISSN
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Volume of the periodical
91
Issue of the periodical within the volume
1
Country of publishing house
US - UNITED STATES
Number of pages
13
Pages from-to
61-73
UT code for WoS article
000455335500006
EID of the result in the Scopus database
2-s2.0-85059522887