Fast Bayesian Algorithms for FPGA Platforms
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F23%3A00571273" target="_blank" >RIV/67985556:_____/23:00571273 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Fast Bayesian Algorithms for FPGA Platforms
Original language description
The abstract describes application of the QRD RLS Lattice algorithm for hand detection based on ultrasound and implemenation of the algorithm on FPGA platform. It discusses the results of implementation in terms of algorithm acceleration, computational time and MFLOP/s.
Czech name
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Czech description
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Classification
Type
O - Miscellaneous
CEP classification
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OECD FORD branch
20205 - Automation and control systems
Result continuities
Project
<a href="/en/project/8A21009" target="_blank" >8A21009: Embedded storage elements on next MCU generation ready for AI on the edge</a><br>
Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů