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EN
ČeštinaEnglish

Integrated Iterative Approach to FPGA Placement

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F02%3A03074683" target="_blank" >RIV/68407700:21230/02:03074683 - isvavai.cz</a>

  • Result on the web

    —

  • DOI - Digital Object Identifier

    —

Alternative languages

  • Result language

    angličtina

  • Original language name

    Integrated Iterative Approach to FPGA Placement

  • Original language description

    FPGA, physical design, placement, routing, delay estimation

  • Czech name

    —

  • Czech description

    —

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

    —

Result continuities

  • Project

    —

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2002

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Field-Programmable Logic and Applications - FPL2002

  • ISBN

    3-540-44108-5

  • ISSN

    —

  • e-ISSN

    —

  • Number of pages

    10

  • Pages from-to

    253-262

  • Publisher name

    Springer

  • Place of publication

    Berlin

  • Event location

    Montpellier

  • Event date

    Sep 2, 2002

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    —