Direct Hardware Implementation of Petri Net Based Model
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F03%3A03088913" target="_blank" >RIV/68407700:21230/03:03088913 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
Direct Hardware Implementation of Petri Net Based Model
Original language description
Direct hardware implementation of Petri net in FPGA.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
<a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the Work in Progress Session
ISBN
3-902457-21-X
ISSN
—
e-ISSN
—
Number of pages
2
Pages from-to
56-57
Publisher name
J. Kepler University - FAW
Place of publication
Linz
Event location
Belek-Antalya
Event date
Sep 1, 2003
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—