Design of Self Checking Circuits Based on FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F03%3A03092667" target="_blank" >RIV/68407700:21230/03:03092667 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Design of Self Checking Circuits Based on FPGA
Original language description
The paper focuses on error detection in circuits implemented in FPGAs using error detection codes(ED codes).
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F03%2F0672" target="_blank" >GA102/03/0672: Research of methods and tools for verification of embedded computer system fault tolerance</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 15th International Conference on Microelectronics
ISBN
977-05-2010-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
378-381
Publisher name
Cairo University
Place of publication
Cairo
Event location
Cairo
Event date
Dec 9, 2003
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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