Direct Implementation of Petri Net Based model in FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F04%3A03099874" target="_blank" >RIV/68407700:21230/04:03099874 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Direct Implementation of Petri Net Based model in FPGA
Original language description
This paper shows that a non-deterministic system modeled by Petri-nets (analyzed and simulated by professional software tools, e.g. Design/CPN, JARP, before its hardware implementation) can be successfully hardware implemented (here in an FPGA). We haveconcentrated to the models with really concurrent actions, with different types of dependencies (mutual exclusion, parallel, scheduled) and their direct hardware implementation. Our Petri-nets model need not be equivalent to a FSM, it means that our Petri-net model can non-deterministically choose a transition to be fired from several enabled ones.
Czech name
Není k dispozici
Czech description
Není k dispozici

Project
<a href="/en/project/GA102%2F04%2F0737" target="_blank" >GA102/04/0737: Modern methods of digital system synthesis</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2004
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04
ISBN
83-89712-15-6
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
31-36
Publisher name
University of Zielona Gora
Place of publication
Zielona Gora
Event location
Dychow
Event date
Sep 15, 2004
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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