Finite State Machine Implementation in FPGAs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03109882" target="_blank" >RIV/68407700:21230/05:03109882 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Finite State Machine Implementation in FPGAs
Original language description
This paper deals with the possibility of the description and decomposition of the finite state machine (FSM). The aim is to obtain better placement of a designed FSM to the selected FPGA. It compares several methods of encoding of the FSM internal stateswith respect to the space (the number of CLB blocks) and time characteristics. It evaluates the FSM benchmarks and seeks for such qualitative properties to choose the best method for encoding before performing all FOUNDATION CAD system algorithms sincethis process is time consuming. The new method for encoding the internal FSM states is presented. All results are verified by experiments.
Czech name
Není k dispozici
Czech description
Není k dispozici
Classification
Type
C - Chapter in a specialist book
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F04%2F0737" target="_blank" >GA102/04/0737: Modern methods of digital system synthesis</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Book/collection name
Design of Embedded Control Systems
ISBN
0-387-23630-9
Number of pages of the result
10
Pages from-to
175-184
Number of pages of the book
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Publisher name
Springer
Place of publication
New York
UT code for WoS chapter
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