Design Retiming in HDL

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03110088" target="_blank" >RIV/68407700:21230/05:03110088 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Design Retiming in HDL

Original language description

This paper deals with an improvement of design timing characteristics by modification at the high abstraction level of the system description. Some synthesis tools such as Synplify Pro provide timing optimizations, called pipelining and retiming. These techniques help the designer unify delay slacks at different inputs, which results in higher system clock frequencies of the produced circuit. Unfortunately these techniques are not available for all devices, for example Atmel FPGAs are not supported. A modification at HDL level is the way how to achieve slight improvement for these devices.

Czech name

Design Retiming in HDL

Czech description

Není k dispozici

Type

A - Audiovisual production

CEP classification

IN - Informatics

OECD FORD branch

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Project

<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2005

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

ISBN

80-01-03201-9

Place of publication

Praha

Publisher/client name

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Version

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Carrier ID

neuvedeno