Cache Emulator for SMP Systems

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A00114522" target="_blank" >RIV/68407700:21230/06:00114522 - isvavai.cz</a>

Result on the web

<a href="http://shimi.webzdarma.cz/vyzkum/workshop06/cache_SMP_workshop.doc" target="_blank" >http://shimi.webzdarma.cz/vyzkum/workshop06/cache_SMP_workshop.doc</a>

DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Cache Emulator for SMP Systems

Original language description

Every modern CPU use a complex memory hierarchy, which consists of levels of cache memories. It is really difficult to predict the behavior of this hierarchy for the given program. The situation is even worse in SMP (symmetric multiprocessing) systems. The Cache emulator (shortly CE) can simulates the behavior of caches inside SMP system and compute the number of cache misses during a computation. All measurements are done in the "off-line" mode on the one CPU; the CE uses own virtual cache memory for the exact simulation. It also means that another CPU activity doesn't influence the behavior of the CE.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

IN - Informatics

OECD FORD branch

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Project

<a href="/en/project/IBS3086102" target="_blank" >IBS3086102: Parallel Algorithms for Large Scale Simulation on PC Clusters</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2006

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of Workshop 2006

ISBN

80-01-03439-9

ISSN

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e-ISSN

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Number of pages

2

Pages from-to

114-115

Publisher name

ČVUT

Place of publication

Praha

Event location

Praha

Event date

Feb 20, 2006

Type of event by nationality

EUR - Evropská akce

UT code for WoS article

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