Implementation of the Backtrace Algorithm in an FPGA

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A00117922" target="_blank" >RIV/68407700:21230/06:00117922 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Implementation of the Backtrace Algorithm in an FPGA

Original language description

The backtrace algorithm for determination of input vectors of combinational circuits on the basis of output vector knowledge and other constraints implemented in an FPGA. Results are carried out for the ISCAS'85 benchmarks.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2006

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of Workshop 2006

ISBN

80-01-03439-9

ISSN

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e-ISSN

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Number of pages

2

Pages from-to

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Publisher name

ČVUT

Place of publication

Praha

Event location

Praha

Event date

Feb 20, 2006

Type of event by nationality

EUR - Evropská akce

UT code for WoS article

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