Subtraction Free Almost Montgomery Inverse in ASIC and FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A00118227" target="_blank" >RIV/68407700:21230/06:00118227 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Subtraction Free Almost Montgomery Inverse in ASIC and FPGA
Original language description
Computation of the multiplicative modular inverse is a frequently used operation that forms a part of various cryptographic algorithms. This paper summarizes our efforts to develop a fast and hardware-efficient algorithm for Almost Montgomery Inverse, which is a central part of the computation of a modular inverse.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of Workshop 2006
ISBN
80-01-03439-9
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
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Publisher name
ČVUT
Place of publication
Praha
Event location
Praha
Event date
Feb 20, 2006
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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