Optimisation of Applications for FPGAs with PowerPC Processor Using Priced Timed Automata

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F08%3A00145321" target="_blank" >RIV/68407700:21230/08:00145321 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Optimisation of Applications for FPGAs with PowerPC Processor Using Priced Timed Automata
Original language description
Some digital signal processing applications can be executed faster by moving parts of application implementation into hardware. Platforms, like Xilinx Virtex-4 4VFX12, allow a user to run software in embedded processor and offload computations to the setof hardware modules. The article deals with optimal schedule synthesis techniques for tasks executed on such platform using Priced Timed Automata and UPPAAL CORA tool. It shows a schedule synthesis techniques minimising makespan or sum of completion times criterion. Moreover, it presents a synthesis methodology considering a fraction of resource capacity, called resource budget and maximization of processor utilization for tasks with bounded period. Case studies and FPGA experiments are finally presented.
Czech name
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Czech description
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Project
<a href="/en/project/FT-TA3%2F044" target="_blank" >FT-TA3/044: *Module solution of FLY-BY-WIRE control system for light, jet aircraft.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
IEEE International Symposium on Industrial Electronics - ISIE 2008
ISBN
978-1-4244-1666-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
Anglia Ruskin University
Place of publication
Cambridge
Event location
Cambridge
Event date
Jun 30, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000266702100190

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