Low Complex Interoperable GNSS Signal Processor and its Performance

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F10%3A00169728" target="_blank" >RIV/68407700:21230/10:00169728 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Low Complex Interoperable GNSS Signal Processor and its Performance
Original language description
The recent development of the GNSS systems and international cooperation resulted in important technical problems of the GNSS systems which are an interoperability and compatibility. In the interoperable receivers the most expensive parts - front ends -can be shared for signals reception of different systems. The unification of the signal processor is also possible with some small performance deterioration but the hardware complexity reduction is considerable. The paper analyses applicability of a classical E-L correlator for processing of various GNSS signals and compare its performance with optimal method. The low complex interoperable processor of software receiver based on a FPGA for the GPS, Galileo and GLONASS systems is proposed. The results oftesting on the Galileo E1 and E5 signals are presented. The last part of the paper proposes architecture of a low cost multi system GNSS receiver based on mass market components.
Czech name
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Czech description
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Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2010 IEEE/ION Position, Location and Navigation Symposium
ISBN
978-1-4244-5037-4
ISSN
2153-358X
e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
IEEE
Place of publication
Piscataway
Event location
Indian Wells, CA
Event date
May 4, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000287515800067

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