Direct Quadrature Frequency Synthesizer Implementation in VHDL
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F10%3A00172998" target="_blank" >RIV/68407700:21230/10:00172998 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Direct Quadrature Frequency Synthesizer Implementation in VHDL
Original language description
In this article we describe a creation, modeling, implementation and simulation of a direct quadrature frequency synthesizer.We describe the process of synthesizer modeling in Matlab in both floating and fixed point arithmetics for later implementation in the VHDL language for FPGA. The complete functional block was implemented in the Xilinx Virtex6 FPGA device attached to analog radio front-end built of Analog Devices evaluation boards. The results on the front-end output was measured, presented and compared with the Matlab model.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Knowledge in Telecommunication Technologies and Optics - KTTO 2010
ISBN
978-80-248-2330-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
VŠB - TUO, FEI, Katedra elektroniky a telekomunikační techniky
Place of publication
Ostrava
Event location
Ostrava
Event date
Dec 9, 2010
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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