A Framework for Memory Contention Analysis in Multi-Core Platforms
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00229868" target="_blank" >RIV/68407700:21230/16:00229868 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1007/s11241-015-9229-9" target="_blank" >http://dx.doi.org/10.1007/s11241-015-9229-9</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/s11241-015-9229-9" target="_blank" >10.1007/s11241-015-9229-9</a>
Alternative languages
Result language
angličtina
Original language name
A Framework for Memory Contention Analysis in Multi-Core Platforms
Original language description
The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core platforms. However, real-time applications have not been able to fully benefit from this transition, as the computational gains offered by multi-cores are often ofset by performance degradation due to shared resources, such as main memory. To efficiently use multi-core platforms for real-time systems, it is hence essential to tightly bound the interference when accessing shared resources. Although there has been much recent work in this area, a remaining key problem is to address the diversity of memory arbiters in the analysis to make it applicable to a wide range of systems. This work addresses this problem of diverse arbiters by proposing a general framework to compute the maximum interference caused by the shared memory bus and its impact on the execution time of the tasks running on the cores, considering different bus arbiters. Our novel approach clearly demarcates the arbiter-dependent and independent stages in the analysis of these upper bounds. The arbiter-dependent phase takes as inputs, the arbiter and the task memory-traffic pattern and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to the contention for the bus. We show that the framework can deal with diverse arbiters by applying it to a memory bus shared by a fixed-priority arbiter, a time-division multiplexing (TDM) arbiter, and an unspecified work-conserving arbiter using applications from the MediaBench test suite. We also experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.
Czech name
—
Czech description
—
Classification
Type
J<sub>x</sub> - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
<a href="/en/project/EE2.3.30.0034" target="_blank" >EE2.3.30.0034: Support of inter-sectoral mobility and quality enhancement of research teams at Czech Technical University in Prague</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
Real-Time Systems
ISSN
0922-6443
e-ISSN
—
Volume of the periodical
52
Issue of the periodical within the volume
3
Country of publishing house
US - UNITED STATES
Number of pages
51
Pages from-to
272-322
UT code for WoS article
000374299100002
EID of the result in the Scopus database
2-s2.0-84930607657