Charge injection circuit designed in 65 nm CMOS technology

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00308220" target="_blank" >RIV/68407700:21230/16:00308220 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21340/16:00308220
Result on the web
<a href="http://www.iworid2016.com/wp-content/uploads/2016/07/ABSTRACTS-BOOK_OK-1.pdf" target="_blank" >http://www.iworid2016.com/wp-content/uploads/2016/07/ABSTRACTS-BOOK_OK-1.pdf</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Charge injection circuit designed in 65 nm CMOS technology
Original language description
Ultra deep submicron CMOS technologies provide enhanced radiation tolerance and possibility to integrate complex electronics in a small area, which makes them attractive for fabrication of pixel front-end chips. Presented work concerns the development of a charge injection circuit using 65 nm CMOS technology. The target application of this circuit is calibration of the pixel front-end chip that is being developed by the RD53 collaboration at CERN. Two prototype chips have been designed and submitted. The first chip contains a 12-bit voltage DAC and the second implements the DAC in a charge injection circuit. The charge injection circuit consists of the following blocks: 12-bit voltage DAC, switch and analogue buffers. In addition, the second chip contains a charge sensitive amplifier and a bank of capacitors representing capacitive load of large pixel array that has been integrated for testing of the charge injection circuit. Design of both chips, as well as circuit simulations, laboratory measurements and studies of radiation tolerance will be presented.
Czech name
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Czech description
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Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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