Functional chaining mechanism allowing definable models of electronic devices
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F17%3A00315208" target="_blank" >RIV/68407700:21230/17:00315208 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=8093250" target="_blank" >http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=8093250</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ECCTD.2017.8093250" target="_blank" >10.1109/ECCTD.2017.8093250</a>
Alternative languages
Result language
angličtina
Original language name
Functional chaining mechanism allowing definable models of electronic devices
Original language description
Fast and stable processing optimized for given simulation problem is essential for any modern simulator. It is characteristic for electronic circuit analysis that complexity of simulation is given by circuit size and used device models. Implementation of electronic device models in program SPICE uses traditional functional paradigm allowing fast computation but further modification of model can be questionable. In this article, we propose modification of standard procedure inserting functional computation layer into the process. It allows on-the-fly modification of standard models and own functional definition during circuit definition without a loss in computational performance. It also gives a possibility of functional chaining mechanism and improves mapping performance of circuit variables to device models.
Czech name
—
Czech description
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Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
<a href="/en/project/TE01020186" target="_blank" >TE01020186: Integrated Satellite and Terrestrial Navigation Technologies Centre</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 23rd European Conference on Circuit Theory and Design
ISBN
978-1-5386-3974-0
ISSN
—
e-ISSN
2474-9672
Number of pages
4
Pages from-to
1-4
Publisher name
IEEE
Place of publication
New Jersey
Event location
Catania
Event date
Sep 4, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000426983700031